Until recently, computers and other electronic devices primarily relied upon single-frequency, single-phase digital clocks. Generating and synthesizing such single-phase clocks, directly or with phase locked locked loops (PLLs) and dividers are straightforward.
New types of processors, power converters, and other electronic devices are increasingly making uses of multi-phase clocks. Multi-phase clocks are clocks having a plurality (2 or more) phases. Various mechanisms have been developed to generate multi-phase clocks, including different oscillators and frequency dividers.
For example, a multi-phase ring oscillator places an even-number of cross-coupling transistors and inverters end-to-end in a ring configuration. The output phases are tapped at the output of each inverter. Four of such inverters will produce a four-phase output.
Digital frequency dividers, sometimes referred to as clock dividers, are used in computer and communications circuits to synthesize clock signals from an input clock signal (input clock). More specifically, a frequency divider is a circuit that divides an input frequency (fin) of an input clock by an integer (n) to produce output clocks each having a different output frequency (fout). The integer is referred to herein as the divider ratio of the circuit, and the frequency of the output clocks is given below in Equation 1:
                    fout        =                              fin            n                    .                                    (                  Equation          ⁢                                          ⁢          1                )            